Generally, clock signals with one or more frequencies are required for many recent integrated circuits. The timing and processing speed of an integrated circuit can be realized according to the clock signals to be used. The operating speed of the circuit system is increased as the frequencies of clock signals thereof increase. Thus, the quality of a clock signal is very important for the circuit system. If the quality of a clock signal is not well maintained, the operating speed of the circuit system may not be increased, or even the whole circuit system fails to operate.
When the quality of clock signals of the circuit system is taken into consideration, in addition to their accuracy, more attention should be paid to the duty cycles thereof. An ideal clock signal 100 shown in FIG. 1 has a duty cycle of 50%. That is to say, this ideal clock signal has alternate high level and low level, and the time spans of the high level and low level are equal.
With increasing development, the circuitries of integrated circuits become more and more complicated. Furthermore, the clock signals used in the integrated circuits must be distributed into a plurality of branches for being transmitted to desired parts of the integrated circuit system so as to be the timing basis for operating the circuit system. However, once the plurality of clock signals are divided side-by-side, the energy of each clock signal is equally divided, and the reduced energy might not be sufficient to drive subsequent sectional circuits. In order to solve the problem, a clock tree circuit having a plurality of buffers 205 shown in FIG. 2 was incorporated into the circuit system so as to enhance the fan-out capability of the clock signals.
FIG. 3 is a schematic circuit block diagram illustrating a buffer applied in a conventional clock tree circuit. The buffer comprises two inverters 300. Each inverter 300 comprises a PMOS transistor 305 and an NMOS transistor 310. The PMOS transistor 305 has a source terminal connected to an applied voltage 315 and a drain terminal connected to the drain terminal of the NMOS transistor 310 so as to form a common output end 330 of this inverter 300. The NMOS transistor 310 has a source terminal connected to a grounding level 320. The gate terminals of the PMOS transistor 305 and the NMOS transistor 310 are connected with each other so as to form a common input end 325 of the inverter 300. If the logic value inputted into this inverter 300 is “1”, the PMOS transistor 305 suspends operations but the NMOS transistor 310 operates. As a result, a logic value “0” is generated and outputted through the output end 330. On the contrary, if the logic value inputted into this inverter 300 is “0”, a logic value “1” is generated and outputted through the output end 330.
As also shown in FIG. 3, these two inverters 300 are connected with each other in series to form a buffer. If a logic value “1” is inputted into the buffer via the input end 325, a logic value “1” is generated and outputted through the output end 335. Whereas, if a logic value “0” is inputted into the buffer via the input end 325, a logic value “0” is generated and outputted through the output end 335. Furthermore, the energy provided by the inverters 300 can be used to enhance the fan-out capability of the clock tree circuit, and thus clock signals will have sufficient energy to drive the next-stage buffers.
Due to the above reasons, the clock signals used in the integrated circuits must be distributed into a plurality of branches by using a plurality of buffers 205 to form the clock tree circuit in FIG. 2. In practice, each buffer 205 has a circuit configuration as that shown in FIG. 3, i.e. a complementary metal-oxide-semiconductor (CMOS) transistor. Due to different electrical properties and different sizes between the PMOS transistor and the NMOS transistor of the CMOS transistor, and parasitic capacitance caused by the clock tree circuit itself and other effects, when an ideal clock signal 200 having a duty cycle of 50% (as shown in FIG. 2) is repeatedly divided, the output clock signal might be somewhat distorted. For example, as can be seen in FIGS. 4(a) and 4(b), either a clock signal 405 with a duty cycle greater than 50% or a clock signal 410 with a duty cycle less than 50% is outputted.
That is to say, the quality of the clock signals might be impaired after the clock signals are repeatedly divided by the clock tree circuit. Therefore, the operating speed of the circuit system may not be increased, or even the whole circuit system fails to operate.